Wearables, sensors, and Internet of Things (IoT) arguably represent the next frontier of computing. They will be characterized by extremely low power and area requirements. In our recent research, we asked the question: are there opportunities for power and area reduction that are unique to these emerging computing platforms. We answered the question in the affirmative and developed several techniques that appear to be very effective. In this talk, I will focus one such technique–symbolic hardware-software co-analysis–that is applicable over a wide class of applications. Through a novel symbolic execution-based approach, we can determine for a given application the gates in the hardware that the application is guaranteed to not touch. This information can then be used to determine application-specific Vmin, determine application-specific peak power, and, build bespoke processors customized to a given application. If time permits, I will also discuss how architectural ideas such bit serial processors and k-hot pipelining may become promising for the IoT applications.
Biography:
Rakesh Kumar is an Associate Professor in the Electrical and Computer Engineering Department at the University of Illinois at Urbana Champaign and a Co-Founder and Chief Architect at Hyperion Core, Inc. He has made contributions in the area of processor design and memory system design that have directly impacted industry and state-of-art. His current research interests are in computer architecture, low power and error resilient computer systems, and approximate computing. He has a B-Tech from IIT Kharagpur and a PhD from University of California at San Diego. He is often seen at a restaurant or hanging out with his very active three-year old.
