For nanotechnology, the device feature size is scaled aggressively, the device is subjected to high order effects impacts (i.e. leakage, process variation and temperature variation). Moreover, the device drive strength is enhanced by strain engineering, the overall device performance is no longer dependent on the transistor channel width and length but also the layout topology. Layout Dependent Effect (LDE) is introduced to predict the circuit behavior since 90nm technology, which includes: Well Proximity Effect (WPE), Length of OD (LOD). OD Spacing Effect (OSE) and Poly Spacing Effect (PSE). Those effects all accounts for layout environment impacts toward circuit performance. With complex circuit layout, the current extraction and simulation model can’t account for all process variations. Therefore the Restricted Design Rules (RDR) are proposed to restrict the layout topology to limit the high order effect impacts and simplify EDA tool implementation. Additional DFM guidelines are introduced to further enhance the device performance with yield improvement.
Currently, the foundry only provides the brief design guideline without detail description; it is difficult for the designer to the guidelines for different circuit implementations. For example, the compact digital standard cell requires minimum channel length to fulfill the performance, power and area requirements. On the other hand, the analog circuit always focuses on accurate circuit performance at various frequencies as well as the noise immunity capability; the area is not the most critical design criteria. Moreover, the circuit designer would like to quantify those guideline electrical impacts with performance, power and area trade-off. In order to resolve those issues, new Layout Validation Monitor (LVM) is developed which is different from conventional Process Control Monitor (PCM), PCM is implemented using simple layout structure which is used to measure the device performance under different process conditions. However, LVM is derived from actual circuit layout and used to perform Silicon-to-Simulation (S2S) correlation, it is not limited to functional yield debug but also the parametric one. It can identify the exact silicon/model mismatch location to investigate the root cause of failure, the results are also used for DFM guideline development. Based on LVM results, this paper recommends some layout enhancement to improve the circuit performance and reduce the process variation for digital standard cell and analog differential pair. In order to resolve those issues, new Layout Validation Monitor (LVM) is developed which is different from conventional Process Control Monitor (PCM), PCM is implemented using simple layout structure which is used to measure the device performance under different process conditions. However, LVM is derived from actual circuit layout and used to perform Silicon-to-Simulation (S2S) correlation, it is not limited to functional yield debug but also the parametric one. It can identify the exact silicon/model mismatch location to investigate the root cause of failure, the results are also used for DFM guideline development. Based on LVM results, this paper recommends some layout enhancement to improve the circuit performance and reduce the process variation for digital standard cell and analog differential pair.
Biography:
Chun-Chen Liu (S’04) received the B.S. degree in Electrical Engineering from the National Cheng Kung University, Taiwan, R.O.C., in 2003. Then he began his M.S./PhD program majoring in Electrical and Computer Engineering from the University of California, San Diego. During that period, he participated in a joined-research with UC Berkeley. From 2007-2010, He was the technical officer of Wireless Info Tech Ltd (acquired by Vance Info, NYSE:VIT). After that, Mr. Liu has served as the technical team leader, managing and leading several research and production development in Samsung, Mstar and Qualcomm. Currently, He is the Chair& CTO of Kneron, San Diego. Mr. Liu was a recipient of the IBM Problem Solving Award based on the use of the EIP tool suite in 2007. Two of his papers were nominated as the Best Paper Award candidates at the IEEE/ACM International Conference on Computer-Aided Design (ICCAD) in 2007 and IEEE International Conference on Compute Design (ICCD) in 2008.
